1. Field of the Invention
The present invention relates to a method of fabricating a CMOS image sensor. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for enhancing the robustness and/or performance of a device, particularly an imaging device.
2. Discussion of the Related Art
Generally, an image sensor is a semiconductor device that transforms an optical image into an electrical charge and/or signal. Semiconductor image sensors are mainly classified into a charge coupled device (hereinafter abbreviated CCD) image sensor and a complementary metal oxide semiconductor (hereinafter abbreviated CMOS) image sensor.
A CCD image sensor commonly consists of a pixel array of photodiodes (PD) arranged in a matrix form to that convert optical signals into electrical signals and/or charges. A plurality of vertical CCDs (VCCDs), provided between columns of photodiodes in the pixel array, transfer charges generated by the photodiodes in the vertical direction to a horizontal CCD (HCCD). The HCCD transfers the charges received from the VCCDs in a horizontal direction to a sense amplifier. The sense amplifier produces electrical signals representative of the charges received from the HCCD.
The above-configured CCD has a complicated driving mechanism, consumes considerable power, and generally involves a complicated fabrication process (e.g., due to a multi-step photolithography process). Further, because it is difficult to integrate with a control circuit, signal processing circuit, analog/digital converting circuit (A/D converter) and other circuitry on a CCD chip, the above-configured CCD is disadvantageous in reducing a size of product.
Recently, attention has been paid to CMOS image sensors as a next generation image sensor that overcome many disadvantages of the CCDs. Like CCD image sensors, CMOS image sensors comprise a pixel array of photodiodes or similar light transducers. However, unlike CCDs, CMOS image sensors incorporate one or more MOS transistors in each photodiode pixel. A control circuit selectively switches the transistors in each pixel to transfer desired photodiode signals to signal processing circuitry. A control circuit, signal processing circuit and other circuitry are commonly integrated onto a CMOS image sensor as peripheral circuits. CMOS image sensors produce images by sequentially detecting electrical signals generated by each unit pixel according to a switching method accomplished in part by configuring a photodiode and MOS transistor(s) within the unit pixel.
The CMOS image sensor, fabricated using CMOS fabrication technology, provides advantages including low power consumption and a relatively simple fabrication process involving a small number of photolithography process steps.
Further, because CMOS image sensors can be integrated with control circuitry, signal processing circuitry, an analog/digital converter and other circuitry on a CMOS sensor chip, CMOS image sensors facilitate product miniaturization.
Hence, in view of their relatively simple fabrication, integration, and low power operation, CMOS image sensors are widely used for various applications, including digital still cameras, digital video cameras and the like.
CMOS image sensors are classified into several types (e.g., 3T type, 4T type, 5T type and the like) according to the number of transistors in each unit pixel. The 3T type CMOS image sensor consists of one photodiode and three transistors. The 4T type CMOS image sensor consists of one photodiode and four transistors. An equivalent circuit and layout of a unit pixel of the 3T type CMOS image sensor are explained with reference to FIGS. 1-3E.
FIG. 1 illustrates an equivalent circuit of a general 3T type CMOS image sensor. FIG. 2 illustrates a layout of a unit pixel of a general 3T type CMOS image sensor. FIGS. 3A to 3E illustrate cross-sectional diagrams of the process of fabricating a CMOS image sensor according to related art.
Referring to FIG. 1, a general 3T type CMOS image sensor consists of one photodiode PD and three NMOS transistors T1, T2, and T3. The cathode of the photodiode PD is connected to the drain of the first NMOS transistor T1 and the gate of the second NMOS transistor T2.
Sources of the first and second NMOS transistors T1 and T2 are connected to a power line that supplies a reference voltage VR. The gate of the first NMOS transistor T1 is connected to a reset line that supplies a reset signal RST.
The source of the third NMOS transistor T3 is connected to the drain of the second NMOS transistor. The drain of the third NMOS transistor T3 is connected to a read circuit (not shown in the drawing) via a signal line. The gate of the third NMOS transistor is connected to a column selection line that supplies a selection signal SLCT.
In accordance with their functions, the first to third NMOS transistors T1, T2, and T3 are referred to as reset, drive and selection transistors Rx, Dx and Sx, respectively.
Referring to FIG. 2, in a unit pixel of a general 3T type CMOS image sensor, an active area 10 is defined. One photodiode 20 is formed on a relatively wide part of the active area 10. Gate electrodes 120, 130 and 140 of the three transistors Rx, Dx, Sx are formed to overlap with remaining portions of the active area 10. Namely, the reset, drive and selection transistors Rx, Dx and Sx are configured with the gate electrodes 120, 130 and 140, respectively.
Impurity ions are implanted into the active area 10, except for the portion of the active area 10 overlapped by the transistor gate electrodes 120, 130, 140, to form photodiode area PD and source/drain regions of the transistors Rx, Dx, Sx, respectively.
Power voltage terminal Vdd is connected to the source/drain regions between the reset and drive transistors Rx and Dx. One source/drain region of the select transistor Sx is connected to the read circuit (not shown in the drawing).
Each of the gate electrodes 120, 130 and 140 is connected to a corresponding signal line (not shown in the drawing). A pad is provided for each signal line to be connected to an external drive circuit (not shown).
A process of forming the signal lines having the pads and processes carried out after completion of the signal line are explained as follows.
FIGS. 3A to 3E are cross-sectional diagrams for explaining a process of fabricating a CMOS image sensor according to a related art.
Referring to FIG. 3A, an insulating layer (e.g. oxide layer) 101, such as a gate insulating layer and/or an insulating interlayer (e.g., an insulator layer between a gate layer and a metal layer, or alternatively, between adjacent layers of metal, in the CMOS image sensor device), is formed on a semiconductor substrate 100. A metal pad 102 is formed on the insulating layer 101 for each of one or more of the signal lines.
Metal pad 102 may be formed with the same material used to form the corresponding gate electrodes 120, 130 or 140 on the same layer. Alternatively, the metal pad 102 may be formed with a different material, such as Al (aluminum), which may connect to a gate electrode via a separate contact.
Corrosion resistance of the metal pad 102 (e.g., comprising Al) may be increased in a later process by surface treatment carried out on a surface of the metal pad 102 by, e.g., UV ozone treatment or solution synthesis. A protective layer 103 may be formed on the insulating layer 101 and the metal pad 102. The protective layer 103 may comprise an oxide or nitride (e.g., of silicon).
Referring to FIG. 3B, a photoresist layer 104 is coated on the protective layer 103. The photoresist layer 104 is then patterned by exposure and development to expose an upper part of the metal pad 102. The protective layer 103 is then selectively etched using the patterned photoresist layer 104 as a mask to form an opening 105 exposing the metal pad 102.
Referring to FIG. 3C, after the patterned photoresist layer 104 has been removed, a first planarizing layer 106 is formed on the protective layer 103. The first planarizing layer 106 is then patterned by photolithography so that the protective layer 106 does not overlap the metal pad 102 or, in many cases, a non-planar portion of protective layer 103.
A color filter layer 107 is then formed on the first planarizing layer 106 corresponding to each photodiode (not shown in the drawing). In this case, each color filter in the color filter layer 107 (which contains a plurality of color filters) is formed by coating a corresponding color resist and by carrying out photolithography using a separate mask for each color filter.
Referring to FIG. 3D, a second planarizing layer 108 is formed over the substrate including the color filter layer 107 and is then patterned by photolithography using a mask so that it does not overlap metal pad 102 or, in many cases, a non-planar portion of protective layer 103. Typically, second planarizing layer 108 does not contact protective layer 103.
Referring to FIG. 3E, microlenses 109 are formed on the second planarizing layer 108 corresponding to the color filters in the color filter layer 107.
A probe test is carried out on the metal pad 102 of the CMOS image sensor to check a contact resistance. If the metal pad 102 passes the probe test, the metal pad 102 is electrically connected to an external drive circuit (not shown).
Thus, the color filter layer 107 includes red, green and blue color filters formed by a plurality of photolithography processes, and separately, a unique microlens 109 over each color filter in the color filter layer 107, formed by a further photolithography process. In this process, if an alignment between the microlenses 109 and the color filter layer 107 deviates from a predetermined range, an image sensor pixel will fail to produce an expected and/or appropriate color. Furthermore, since the microlenses 109 are formed by reflow of a microlens resist at 150˜200° C., the microlenses 109 are sensitive to the temperature and thickness of the microlens resist.
These process variables (e.g., temperature and thickness of the microlens resist, photolithography alignment tolerances and variability) affect the alignment between the microlenses 109 and the color filters in the color filter layer 107. Misalignment reduces incident light throughput to the color filters and, subsequently, to the photodiodes.
Moreover, the open metal pad 102, which is exposed to photolithography development solution(s) through multi-step photolithography processes, is vulnerable to chemical attack, which may result in failure during probe test, or which may generate metal fragments from the attacked metal pad 102. Metal fragments generated from the probe test may be transferred to the microlenses and may cut off or reflect light incident on the color filters and photodiodes, resulting in a pixel noise defect.